π² WIA-SEMI-001 Simulator
Interactive Semiconductor Design Flow Environment
π¬ RTL Design
β Verification
β‘ Synthesis
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RTL Design Editor
Module Configuration
Module Name:
HDL Language:
Verilog
SystemVerilog
VHDL
Design Type:
Combinational Logic
Sequential Logic
Finite State Machine
Pipeline
RTL Code
module counter #( parameter WIDTH = 8 )( input wire clk, input wire rst_n, input wire enable, output reg [WIDTH-1:0] count ); always @(posedge clk or negedge rst_n) begin if (!rst_n) count <= {WIDTH{1'b0}}; else if (enable) count <= count + 1'b1; end endmodule
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Verification Environment
Testbench Configuration
Verification Method:
Directed Testing
Constrained-Random
UVM Testbench
Formal Verification
Simulation Cycles:
Coverage Goals (%):
Run Simulation
Coverage Report
Waveform Viewer
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0%
Functional Coverage
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Assertions Passed
Logic Synthesis
Synthesis Configuration
Target Technology:
TSMC 5nm
Samsung 7nm
Intel 14nm
TSMC 28nm
Clock Frequency (MHz):
Optimization Goal:
Balanced
Minimize Area
Minimize Power
Maximize Performance
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Timing Report
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Synthesis Report
Quality of Results (QoR)
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Area (Β΅mΒ²)
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Power (mW)
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Physical Design & Layout
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Die Height (Β΅m):
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