Dynamic Random Access Memory (DRAM) is the dominant technology for main memory in computing systems. DRAM stores each bit of data as an electrical charge in a capacitor, paired with an access transistor in what is called a 1T1C (one transistor, one capacitor) cell structure. This simple architecture enables high density and low cost per bit, making DRAM ideal for applications requiring large memory capacities.
The term "dynamic" refers to the need for periodic refresh operations. Because capacitors naturally leak charge over time, DRAM cells must be refreshed every 32-64 milliseconds to maintain data integrity. Modern DRAM controllers handle refresh transparently, but this overhead impacts performance and power consumption. Despite this limitation, DRAM's density advantages make it the preferred choice for main memory.
Samsung and SK Hynix are global leaders in DRAM technology, pushing the boundaries of process scaling. Modern DRAM is manufactured using process nodes below 10 nanometers (1α, 1β, 1γ generations), with Samsung achieving 14nm-class production and SK Hynix reaching 1bnm (below 10nm). These advances require extreme ultraviolet (EUV) lithography and innovative materials.
| Generation | Year | Data Rate (MT/s) | Bandwidth (GB/s) | Voltage | Key Features |
|---|---|---|---|---|---|
| DDR | 2000 | 200-400 | 1.6-3.2 | 2.5V | Double data rate |
| DDR2 | 2003 | 400-800 | 3.2-6.4 | 1.8V | 4-bit prefetch |
| DDR3 | 2007 | 800-1600 | 6.4-12.8 | 1.5V | 8-bit prefetch |
| DDR4 | 2014 | 1600-3200 | 12.8-25.6 | 1.2V | Bank groups, DBI |
| DDR5 | 2020 | 3200-6400+ | 25.6-51.2+ | 1.1V | Dual channel, on-die ECC |
DDR5, the latest generation, doubles bandwidth compared to DDR4 while improving power efficiency. Samsung and SK Hynix both produce DDR5 modules exceeding 6400 MT/s, with roadmaps extending to 8400 MT/s and beyond. DDR5 introduces on-die error correction code (ECC) for improved reliability and dual-channel architecture per module for better parallelism.
NAND flash memory has revolutionized data storage through its combination of non-volatility, high density, and reasonable cost. Unlike DRAM, NAND retains data without power by trapping electrons in a floating gate or charge trap structure. This makes NAND ideal for storage applications including SSDs, USB drives, memory cards, and embedded storage in smartphones.
NAND flash is organized into pages (typically 16KB) for read/write operations and blocks (typically 4MB) for erase operations. This asymmetric access pattern—where writes must be preceded by block erasures—requires sophisticated firmware (Flash Translation Layer) to manage wear leveling, garbage collection, and bad block management.
2D Planar NAND (1989-2015): Traditional NAND flash scaled through process node shrinking, reaching 15-16nm before hitting physical limits. As cells became smaller, charge storage became less reliable and endurance decreased.
3D NAND / V-NAND (2013-Present): Samsung pioneered 3D NAND technology, stacking memory cells vertically to increase density without further process scaling. Modern 3D NAND exceeds 200 layers, with Samsung achieving 236 layers and SK Hynix reaching 238 layers. This vertical scaling has enabled multi-terabyte SSDs at consumer-friendly prices.
| Technology | Bits/Cell | Write Endurance | Performance | Cost/GB | Use Cases |
|---|---|---|---|---|---|
| SLC (Single-Level Cell) | 1 | 100,000 cycles | Fastest | Highest | Enterprise, industrial |
| MLC (Multi-Level Cell) | 2 | 10,000 cycles | Fast | High | Client SSDs |
| TLC (Triple-Level Cell) | 3 | 3,000 cycles | Moderate | Medium | Consumer SSDs |
| QLC (Quad-Level Cell) | 4 | 1,000 cycles | Slower | Lowest | Read-intensive storage |
Static RAM (SRAM) uses six transistors per bit arranged as cross-coupled inverters to create a bistable circuit. Once set to 0 or 1, an SRAM cell maintains its state without refresh as long as power is supplied. This makes SRAM much faster than DRAM (1-10ns access time vs. 50-100ns for DRAM) and ideal for CPU cache memory.
Modern processors incorporate multiple levels of SRAM cache: L1 cache (32-128KB, 1-2ns latency), L2 cache (256KB-1MB, 3-5ns latency), and L3 cache (4-64MB, 10-20ns latency). This cache hierarchy provides the performance benefits of SRAM while the bulk of system memory uses more cost-effective DRAM.
SRAM's main disadvantages are low density (requiring 6 transistors per bit versus 1T1C for DRAM) and high cost (typically 10-100x more expensive per bit). As a result, SRAM is limited to cache applications where speed justifies the cost premium. Advanced processors may dedicate 30-40% of their die area to SRAM cache.
High Bandwidth Memory represents a paradigm shift in memory architecture, stacking multiple DRAM dies vertically and connecting them to a logic base die through thousands of Through-Silicon Vias (TSVs). This 3D stacking enables much wider memory interfaces (1024-2048 bits) compared to traditional DRAM (64 bits), dramatically increasing bandwidth.
SK Hynix is the dominant supplier of HBM for AI accelerators, providing HBM to NVIDIA, AMD, and other GPU manufacturers. Samsung also produces HBM3E with industry-leading bandwidth specifications. HBM has become essential for AI training, where memory bandwidth often limits performance more than computational power.
| Generation | Bandwidth/Stack | Capacity/Stack | Interface Width | Voltage | Applications |
|---|---|---|---|---|---|
| HBM1 | 128 GB/s | 4 GB | 1024-bit | 1.2V | Graphics, HPC |
| HBM2 | 256 GB/s | 8 GB | 1024-bit | 1.2V | AI training, datacenter |
| HBM2E | 460 GB/s | 16 GB | 1024-bit | 1.2V | AI, deep learning |
| HBM3 | 819 GB/s | 24 GB | 1024-bit | 1.1V | Next-gen AI, HPC |
| HBM3E | 1152 GB/s | 36 GB | 1024-bit | 1.1V | LLM training, inference |
The memory industry is actively developing next-generation technologies that aim to combine the best characteristics of volatile and non-volatile memory: the speed of DRAM with the persistence of Flash.
MRAM stores data using magnetic tunnel junctions (MTJ) that exhibit different electrical resistance depending on the relative magnetization of two ferromagnetic layers. Spin-transfer torque MRAM (STT-MRAM) uses spin-polarized current to switch magnetization, enabling high-density integration. MRAM offers non-volatility, fast access (10-20ns), virtually unlimited endurance (10^15 cycles), and radiation hardness. Samsung and SK Hynix are both investing in MRAM for embedded applications and potential DRAM replacement.
PCM exploits the large resistance difference between amorphous (high resistance) and crystalline (low resistance) phases of chalcogenide glass materials like Ge₂Sb₂Te₅. Electrical current heats the material to switch between phases, enabling non-volatile data storage. PCM offers multi-level cell capability (storing multiple bits per cell), good scalability, and moderate endurance. Intel and Micron developed 3D XPoint (Optane) using phase-change technology, though Intel has since exited the business.
ReRAM changes resistance through formation and dissolution of conductive filaments in a metal-oxide dielectric. A metal-insulator-metal structure can switch between high-resistance (filament broken) and low-resistance (filament formed) states. ReRAM offers simple two-terminal structure, low power operation, fast switching (sub-nanosecond), and potential for dense 3D cross-point arrays. Korean companies are exploring ReRAM for neuromorphic computing and storage-class memory.
Choosing the appropriate memory technology for a given application requires careful consideration of multiple factors: performance requirements, capacity needs, power constraints, cost targets, and reliability specifications. No single memory type excels at everything, which is why computing systems employ a hierarchy of different memory technologies.
For high-performance computing and AI applications, HBM provides unmatched bandwidth to feed hungry processors. Data center servers require large-capacity DDR5 DRAM for main memory. Consumer devices use LPDDR for power efficiency. Storage systems employ NAND flash for capacity and persistence. Each application has an optimal memory solution based on its specific requirements.